RISC-V

What:

It’s an open-source, Instruction Set Architecture. While architectures like x86 are commercial, RISC is royalty free - making it really popular in academia. You code in assembly (albeit a different kind to the MIPS one). It’s:

• Simple
• Modular
• Has 32 general purpose registers (x0 -> x31 - 0x is reserved for $0$.).
• The stack, like in MIPS, starts at high values and grows downwards.

Remember: A word is 32 bits (i.e. 4 bytes)

Registers uses

Register Number	Name	Description	Saver
x0	zero	hardwired zero	-
x1	ra	return address	Caller
x2	sp	stack pointer	Callee
x3	gp	global pointer	-
x4	tp	thread pointer	-
x5 - x7	t0 - t2	temporary registers	Caller
x8	s0 / fp	saved registers / frame pointer	Callee
x9	s1	saved registers	Callee
x10 - x11	a0 - a1	function arguments / return values	Caller
x12 - x17	a2 - a7	function arguments	Caller
x18 - x27	s2 - s11	saved registers	Callee
x28 - x31	t3 - t6	temporary registers	Caller